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| Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T FEATURES * 'Trench' technology * Low on-state resistance * Fast switching * Low thermal resistance SYMBOL d QUICK REFERENCE DATA VDSS = 200 V ID = 5.2 A g RDS(ON) 400 m s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor using Trench technology, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHX9NQ20T is supplied in the SOT186A (FPAK) conventional leaded package PINNING PIN 1 2 3 case gate drain source isolated DESCRIPTION SOT186A (FPAK) case SOT186 (FPAK) case 123 123 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Ths = 25 C; VGS = 10 V Ths = 100 C; VGS = 10 V Ths = 25 C Ths = 25 C MIN. - 55 MAX. 200 200 20 5.2 3.3 21 25 150 UNIT V V V A A A W C November 2000 1 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 7.2A; tp = 100 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 10 V; refer to fig;15 MIN. MAX. 93 UNIT mJ IAS - 8.7 A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-hs Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT186A package, in free air TYP. MAX. UNIT 55 5 K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance Forward transconductance Gate source leakage current Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 4.5 A Tj = 150C VDS = 25 V; ID = 4.5 A VGS = 10 V; VDS = 0 V VDS = 200 V; VGS = 0 V Tj = 150C ID = 9 A; VDD = 160 V; VGS = 10 V MIN. 200 178 2 1 3.8 TYP. MAX. UNIT 3 300 6 10 0.05 24 4 12 8 19 25 15 4.5 7.5 959 93 54 4 6 400 0.94 100 10 500 V V V V V m S nA A A nC nC nC ns ns ns ns nH nH pF pF pF VDD = 100 V; RD = 10 ; VGS = 10 V; RG = 5.6 Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz November 2000 2 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 9 A; VGS = 0 V IF = 9 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. MAX. UNIT 0.85 92 0.5 8.7 35 1.2 A A V ns C ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 C unless otherwise specified SYMBOL Visol PARAMETER R.M.S. isolation voltage from all three terminals to external heatsink Repetitive peak voltage from all three terminals to external heatsink Capacitance from pin 2 to external heatsink CONDITIONS SOT186A package; f = 50-60 Hz; sinusoidal waveform; R.H. 65%; clean and dustfree SOT186 package; R.H. 65%; clean and dustfree f = 1 MHz MIN. TYP. MAX. 2500 UNIT V Visol - 1500 V Cisol - 10 - pF November 2000 3 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating with heatsink compound 10 Transient thermal impedance, Zth j-a (K/W) D = 0.5 0.2 1 0.1 0.05 0.02 0.1 single pulse 0.01 1E-06 0 20 40 60 80 Ths / C 100 120 140 1E-05 1E-04 1E-03 1E-02 1E-01 Pulse width, tp (s) 1E+00 1E+01 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) Normalised Current Derating with heatsink compound Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) Tj = 25 C VGS = 10V 8V 5.5 V 6V 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% 10 9 8 7 6 5 4 3 2 1 0 5V 4.5 V 0 20 40 60 80 Ths / C 100 120 140 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); VGS 10 V Peak Pulsed Drain Current, IDM (A) Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS) 100 0.5 Drain-Source On Resistance, RDS(on) (Ohms) 4.5 V 5V Tj = 25 C RDS(on) = VDS/ ID 10 tp = 10 us 100us 1 D.C. 1 ms 10 ms 100 ms 0.1 1 10 100 Drain-Source Voltage, VDS (V) 1000 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 1 5.5 V 6V VGS = 10V 8V 2 3 4 5 6 Drain Current, ID (A) 7 8 9 10 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID) November 2000 4 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T 10 9 8 7 6 5 4 3 2 1 0 0 Drain current, ID (A) 4.5 4 3.5 3 2.5 2 Threshold Voltage, VGS(TO) (V) 150 C Tj = 25 C 1.5 1 0.5 0 1 2 3 4 Gate-source voltage, VGS (V) 5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) Transconductance, gfs (S) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1.0E-01 Drain current, ID (A) 1.0E-02 Tj = 25 C 1.0E-03 minimum typical 150 C 1.0E-04 maximum 1.0E-05 1.0E-06 0 1 2 3 4 5 ID / (A) 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C 2.5 Normalised On-state Resistance Capacitances, Ciss, Coss, Crss (pF) 10000 2 Ciss 1.5 1000 1 Coss 100 0.5 Crss 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 Junction Temperature, Tj C 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz November 2000 5 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gate-source voltage, VGS (V) ID = 9 A Tj = 25 C VDD = 40 V 10 Maximum Avalanche Current, IAS (A) 25 C VDD = 160 V 1 Tj prior to avalanche = 150 C 0 5 10 15 20 Gate charge, QG (nC) 25 30 35 0.1 0.001 0.01 0.1 Avalanche time, tAV (ms) 1 10 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load 10 9 8 7 6 5 4 3 2 1 0 Source-Drain Diode Current, IF (A) VGS = 0 V 150 C Tj = 25 C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Source-Drain Voltage, VSDS (V) 1 1.1 1.2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj November 2000 6 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T MECHANICAL DATA Dimensions in mm Net Mass: 2 g Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 SOT186A E P q D1 T A A1 D j L2 b1 L b2 L1 K Q 1 2 b e e1 3 wM c 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.6 4.0 A1 2.9 2.5 b 0.9 0.7 b1 1.1 0.9 b2 1.4 1.2 c 0.7 0.4 D 15.8 15.2 D1 6.5 6.3 E 10.3 9.7 e 2.54 e1 5.08 j 2.7 2.3 K 0.6 0.4 L L1 L2 max. 3 (1) P 3.2 3.0 Q 2.6 2.3 q 3.0 2.6 T (2) w 0.4 14.4 3.30 13.5 2.79 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are 2.5 x 0.8 max. depth OUTLINE VERSION SOT186A REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.16. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 2000 7 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T MECHANICAL DATA Dimensions in mm Net Mass: 2 g Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 exposed tabs SOT186 E E1 P m A A1 q D1 D L1 Q L L2 b1 1 2 b e e1 3 wM c 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.4 4.0 A1 2.9 2.5 b 0.9 0.7 b1 1.5 1.3 c 0.55 0.38 D 17.0 16.4 D1 7.9 7.5 E 10.2 9.6 E1 5.7 5.3 e 2.54 e1 5.08 L 14.3 13.5 L1(1) 4.8 4.0 L2 10 m 0.9 0.5 P 3.2 3.0 Q 1.4 1.2 q 4.4 4.0 w 0.4 Note 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. OUTLINE VERSION SOT186 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.17. SOT186; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 2000 8 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 2000 9 Rev 1.100 |
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